Memo
To:Dr.
Mellor
From:David
Calarco, Eli Baca, Mark Jenne, and Joe Salisbury
Date:10/13/2008
Re:Current
Status of Final Project
AFTER MILESTONE 2
Based on the requirements
of milestone’s one and two our team has first and foremost developed
an all encompassing and robust assembly language with the corresponding
machine language interpretation. Utilizing these instruction sets we
were able to generate three sample programs, one of which was the required
Euclid’s Algorithm, while the others were sample programs that encompassed
the instructions not used in the Euclid program.
Once this was complete
we translated all of our Assembly code language into the register transfer
language description. Breaking down our instructions into this language
format, our team was able to determine the necessary elements of the
data path that will be required to implement our design. With this knowledge
each element of the data path was broken down into its input, output,
and control signals. Each signal was then described, both in an English
translation as well as in the required number of bits.
With the completion
of the steps above both of the required milestones were completed. Our
team however has already begun to actually develop a schematic of these
elements to create our processor design. We have not yet completed this
design and still need to work out a few issues, but overall the data
path is beginning to come together. Once we have this design complete,
our team will begin to generate and test each element within the Xilinx
program. Then, once each element is working properly and is tested,
we can begin to integrate them together and debug to create our processor.
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